SEMICONDUCTOR WAFERS WITH THROUGH SUBSTRATE VIAS AND BACK METAL, AND METHODS OF FABRICATION THEREOF

摘要

An embodiment of a semiconductor wafer includes a semiconductor substrate, a plurality of through substrate vias (TSVs), and a conductive layer. The TSVs extend between first and second substrate surfaces. The TSVs include a first subset of trench via(s) each having a primary axis aligned in a first direction, and a second subset of trench via(s) each having a primary axis aligned in a second and different direction. The TSVs form an alignment pattern in an alignment area of the substrate. The conductive layer is directly connected to the second substrate surface and to first ends of the TSVs. Using the TSVs for alignment, the conductive layer may be patterned so that a portion of the conductive layer is directly coupled to the TSVs, and so that the conductive layer includes at least one conductive material void (e.g., in alignment with a passive component at the first substrate surface).

主权项

1. A semiconductor wafer comprising:
a semiconductor substrate having a first substrate surface and a second substrate surface; a plurality of first through substrate vias extending between the first and second substrate surfaces, wherein the plurality of first through substrate vias includes a first subset of one or more trench vias each having a primary axis aligned in a first direction, and a second subset of one or more trench vias each having a primary axis aligned in a second direction that is different from the first direction, and the plurality of first through substrate vias form an alignment pattern in an alignment area of the substrate; and a conductive layer directly connected to the second substrate surface and to first ends of the plurality of first conductive through substrate vias.