发明名称 ANALOG MULTIPLEXER CORE CIRCUIT AND ANALOG MULTIPLEXER CIRCUIT
摘要 This analog multiplexer core circuit (120A) is provided with: a differential pair (121) including two transistors (Q1, Q2); a differential pair (122) including two transistors (Q3, Q4); a differential pair (123) including two transistors (Q5, Q6); and a constant current source (124) which causes a current (IEE) to flow. The analog multiplexer core circuit (120A) multiplexes two analog signals (Ain1, Ain2) and outputs a time-multiplexed analog signal (Aout). An emitter resistance (REA1, REA2, REA3, REA4) is connected to each transistor (Q1, Q2, Q3, Q4). Here, the relational expression "REA·IEE≥amplitude of input analog signal" is satisfied. By this means the linear response input range of the differential pairs (121, 122) is broadened, and response linearity can be ensured.
申请公布号 WO2017014262(A1) 申请公布日期 2017.01.26
申请号 WO2016JP71385 申请日期 2016.07.21
申请人 NIPPON TELEGRAPH AND TELEPHONE CORPORATION 发明人 NAGATANI,Munehiko;NOSAKA,Hideyuki
分类号 H03K17/62;H03F3/45;H04L27/36 主分类号 H03K17/62
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