HYBRID PROGRAMMABLE MANY-CORE DEVICE WITH ON-CHIP INTERCONNECT

摘要

The present invention provides a hybrid programmable logic device which includes a programmable field programmable gate array logic fabric and a many-core distributed processing subsystem. The device integrates both a fabric of programmable logic elements and processors in the same device, i.e., the same chip. The programmable logic elements may be sized and arranged such that place and route tools can address the processors and logic elements as a homogenous routing fabric. The programmable logic elements may provide hardware acceleration functions to the processors that can be defined after the device is fabricated. The device may include scheduling circuitry that can schedule the transmission of data on horizontal and vertical connectors in the logic fabric to transmit data between the programmable logic elements and processor in an asynchronous manner.

主权项

1. A hybrid programmable logic device comprising:
a processor comprising fixed logic elements, wherein in the processor is disposed in a first layer; a programmable logic element disposed in the first layer; and interface circuitry that delivers signal from the programmable logic element to the processor, the interface circuitry comprising:
an input multiplexor coupled to the programmable logic element that receives the signal;an interface buffer that buffers the signal from the input multiplexor; andan interface port coupled to the processor that receives the signal from the interface buffer.