发明名称 シミュレーション装置、シミュレーション方法、およびシミュレーションプログラム
摘要 A simulation apparatus includes a memory, and a second processor configured to detect an internal state of the first processor in the operation simulation, when a target block in the operation simulation changes, the target block being included in blocks obtained by dividing code of the program, generate association information in which the internal state detected by the detecting section and performance values of instructions included in the target block in the detected internal state are associated with each other, and execute an execution code that allows a performance value when the first processor executes the target block to be calculated based on the association information, by using the internal state detected and the association information generated for the target block, to thereby calculate a performance value when the first processor executes the target block.
申请公布号 JP6064765(B2) 申请公布日期 2017.01.25
申请号 JP20130087874 申请日期 2013.04.18
申请人 富士通株式会社 发明人 タシ デビッド;池 敦
分类号 G06F11/36;G06F9/38;G06F9/455 主分类号 G06F11/36
代理机构 代理人
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