发明名称 静電容量素子及び共振回路
摘要 PROBLEM TO BE SOLVED: To stably manufacture a capacitance element that suppresses capacitance variation due to misalignment of electrodes that face each other across a dielectric layer so as to have a desired capacitance.SOLUTION: A capacitance element comprises: a dielectric layer 10; a first electrode formed on an upper surface 10a of the dielectric layer 10; and a lower electrode 12 formed on a lower surface 10b opposite to the upper surface 10a of the dielectric layer 10. An upper electrode 11 and the lower electrode 12 are shaped to ensure that the area of a counter electrode region between the first electrode 11 and the second electrode 12 does not vary, even if the upper electrode 11 is misaligned with respect to the lower electrode 12 relatively in a predetermined direction. Even if misalignment occurred, a projected pattern when an electrode portion 11a is projected on a plane on the opposite side and a terminal portion 12b do not overlap with each other, and a projected pattern when a terminal portion 11b is projected on a plane on the opposite side and an electrode portion 12a do not overlap each other.
申请公布号 JP6067783(B2) 申请公布日期 2017.01.25
申请号 JP20150112882 申请日期 2015.06.03
申请人 デクセリアルズ株式会社 发明人 管野 正喜;横田 敏昭;羽生 和隆;渡辺 誠;佐藤 則孝
分类号 H01G7/06 主分类号 H01G7/06
代理机构 代理人
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