Sampling circuit with reduced metastability exposure

摘要

A sampling circuit uses an input stage to sample an input signal and a secondary evaluation stage to maintain the output state of the input stage. Once the input stage transitions at a clock transition, the secondary evaluation stage uses regenerative feedback devices to hold the state to help ensure the sampling circuit only switches once during an evaluation.

主权项

1. A sampling circuit comprising:
a first circuit to sample and hold input data responsive to a transition of a clock signal and to generate an output responsive to the data, wherein the output of the first circuit includes a set and a reset signal; the first circuit including,
a first inverter having an input coupled to an inverted set signal node and the set signal;a second inverter having an input coupled to an inverted reset signal node and supplying the reset signal;third and fourth inverters cross coupled to hold a state corresponding to the input data sampled by the first circuit, the third inverter supplying the inverted set signal node and the fourth inverter supplying the inverted reset signal node; and a secondary evaluation circuit to help maintain the state of the first circuit after the transition of the clock signal; the secondary evaluation circuit further including,
a first evaluation transistor having a first current carrying node coupled to the inverted set signal node and a gate coupled to the set signal node;a second evaluation transistor having a first current carrying node coupled to the inverted reset signal node and a gate coupled to the reset signal node; anda third evaluation transistor having a first current carrying node coupled to second current carrying nodes of the first and second evaluation transistors, the third evaluation transistor having a gate coupled to the clock signal and a second current carrying node coupled to ground.