Random access memory with pseudo-differential sensing

摘要

Embodiments herein describe DRAM that includes storage circuitry coupled between complementary bit lines which are in turn coupled to the same sense amplifier. The storage circuitry includes a transistor and a storage capacitor coupled in series. The gate of the transistor is coupled to a word line which selectively couples the storage capacitor to one of the complementary bit lines. Because the capacitor is coupled to both of the bit lines, when reading the data stored on the capacitor, the charge on the capacitor causes current to flow from one of the bit lines into the other bit line which causes a voltage difference between the complementary bit lines. Put differently, both ends of the capacitor are electrically coupled to bit lines thereby generating a larger voltage difference between the bit lines when reading data from the storage capacitors.

主权项

1. A dynamic random access memory (DRAM), comprising:
a first bit line and a second bit line, wherein the first and second bit lines form a complementary pair of bit lines coupled with a sense amplifier,
wherein the first and second bit lines are disposed, at least partially, on a common plane; a storage capacitor having a first node coupled with the first bit line; and a transistor comprising a gate coupled with a word line, wherein the transistor comprises a second node coupled with a third node of the storage capacitor and a fourth node coupled with the second bit line, wherein the storage capacitor and the transistor are disposed in a vertical arrangement extending in a direction perpendicular to the common plane; and wherein the sense amplifier is configured to evaluate a voltage difference between the first and second bit lines to determine a data bit stored in the storage capacitor.