Capacitor and method for making same

摘要

A system-on-chip (SOC) device comprises a first capacitor in a first region, a second capacitor in a second region, and may further comprise a third capacitor in a third region, and any additional number of capacitors in additional regions. The capacitors may be of different shapes and sizes. A region may comprise more than one capacitor. Each capacitor in a region has a top electrode, a bottom electrode, and a capacitor insulator. The top electrodes of all the capacitors are formed in a common process, while the bottom electrodes of all the capacitors are formed in a common process. The capacitor insulator may have different number of sub-layers, formed with different materials or different thickness. The capacitors may be formed in an inter-layer dielectric layer or in an inter-metal dielectric layer. The regions may be a mixed signal region, an analog region, a radio frequency region, a dynamic random access memory region, and so forth.

主权项

1. An integrated circuit device comprising:
a semiconductor substrate; an isolation region extending into the semiconductor substrate; a polysilicon layer over and contacting the isolation region; a silicide layer over and contacting the polysilicon layer; a first capacitor in a first region of a chip, the first capacitor comprising:
a first and a second bottom contact plug, each being over and contacting the silicide layer;a first bottom electrode comprising a first cylinder-shaped part and a second cylinder-shaped part, wherein a first bottom portion of the first cylinder-shaped part and a second bottom portion of the second cylinder-shaped part are over and contacting the first and the second bottom contact plugs, respectively;a first capacitor insulator overlying and contacting the first bottom electrode, wherein the first capacitor insulator is formed of a first material;a first top electrode overlying and contacting the first capacitor insulator; a second capacitor in a second region of the chip, the second capacitor comprising:
a second bottom electrode;a second capacitor insulator overlying and directly contacting the second bottom electrode, wherein the second capacitor insulator comprises:
a first sub-layer formed of a second material over and directly contacting the second bottom electrode;a second sub-layer formed of the first material over and directly contacting the first sub-layer; anda second top electrode overlying and directly contacting the second capacitor insulator; and a third capacitor in a third region of the chip, the third capacitor comprising:
a third bottom electrode, wherein the first bottom electrode, the second bottom electrode, and the third bottom electrode are substantially at a same level, and are formed of a same material;a third capacitor insulator comprising:
a third sub-layer formed of a third material overlying and directly contacting the third bottom electrode;a fourth sub-layer formed of the second material overlying and directly contacting the third sub-layer; anda fifth sub-layer formed of the first material overlying and directly contacting the fourth sub-layer; anda third top electrode overlying and directly contacting the third capacitor insulator, wherein the first top electrode, the second top electrode, and the third top electrode have a same thickness, and are formed of a same material.