发明名称 TIME DOMAIN INTEGRATED TEMPERATURE SENSOR
摘要 A time domain integrated temperature sensor described by the present invention adopts a shaped clock signal to control the charging time of capacitors, so that the capacitors generate charging time delay signals related to the cycle of an input clock, and a pulse signal related to pulse width, temperature and the cycle of the input clock is generated through logical XOR (Exclusive OR) operation on a time delay signal generated when the capacitors are charged by one way of PTAT (Proportional To Absolute Temperature) current in an above control manner and a time delay signal generated when the capacitors are charged by one way of CTAT (Complementary To Absolute Temperature) current in the same manner; then, the same input clock signal is adopted for quantifying the pulse width of the pulse signal, the relevance of the obtained quantization result and the cycle of the input clock is completely offset, namely, an output value of the temperature sensor is unrelated to the input clock signal, thereby solving the problem that the reading of the existing time domain integrated temperature sensor is inconsistent as the cycle of the clock signal changes and improving the precision of the time domain integrated temperature sensor to a certain degree.
申请公布号 US2017016776(A1) 申请公布日期 2017.01.19
申请号 US201615277033 申请日期 2016.09.27
申请人 Excelio Technology (Shenzhen) Co.,Ltd. ;Wuxi Excelio Technology CO., Ltd. 发明人 Ma Bill;Wu Patrick,Bian;Han Fuqiang
分类号 G01K3/04;H03K19/21;G05F1/46;H03K17/687;H03K5/153;G01K7/01;H03K21/02 主分类号 G01K3/04
代理机构 代理人
主权项 1. A time domain integrated temperature sensor, comprising a PTAT (Proportional To Absolute Temperature) time delay circuit, a CTAT (Complementary To Absolute Temperature) time delay circuit, an XOR (Exclusive OR) gate and a counter, wherein two input ends of the XOR gate are respectively connected to an output end of the PTAT time delay circuit and an output end of the CTAT time delay circuit, an output end of the XOR gate is connected with an enable end of the counter, and a clock signal input end of the counter is connected to a clock input port of the temperature sensor; the PTAT time delay circuit comprises a PTAT current generation circuit, a first capacitor, a first switch and a first level-detection circuit, an output end of the PTAT current generation circuit is connected to a positive end of the first capacitor, the first switch and an input end of the first level-detection circuit, the first capacitor and the first switch are connected with each other in parallel and then connected to the ground, and an output end of the first level-detection circuit is connected to a first input end of the XOR gate; the CTAT time delay circuit comprises a CTAT current generation circuit, a second capacitor, a second switch and a second level-detection circuit, an output end of the CTAT current generation circuit is connected to a positive end of the second capacitor and the second switch, an input end of the second level-detection circuit, the second capacitor and the second switch are connected with each other in parallel and then connected to ground, and an input end of the second level-detection circuit is connected to a second input end of the XOR gate; the output end of the PTAT current generation circuit is connected with a first switch unit, an output end of the first switch unit is connected to the positive end of the first capacitor, and a control end of the first switch unit is connected to the clock input port of the temperature sensor through a pulse shaping circuit; the output end of the CTAT current generation circuit is connected with a second switch unit, an output end of the second switch unit is connected to the positive end of the second capacitor, and a control end of the second switch unit is connected to the clock input port of the temperature sensor through the pulse shaping circuit; an input end of the pulse shaping circuit is connected to the clock input port of the temperature sensor, an output end of the pulse shaping circuit is connected to the control end of the first switch unit and the control end of the second switch unit respectively, the clock signal input end of the counter is used for shaping an input clock signal into a square wave signal with the same cycle with the input clock signal, the time of high voltage-level of the square wave signal within the cycle is a constant time, the square wave signal is used for controlling switching on and off of the first switch unit and the second switch unit, the square wave signal is also taken as a clock of the counter to count during high voltage-level of a pulse signal, and the counting result is a quantization result of the pulse width of the pulse signal.
地址 Shenzhen CN
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