发明名称 D/A変換回路
摘要 PROBLEM TO BE SOLVED: To effectively remove noise even if common mode noise is superimposed on an input bit-added voltage.SOLUTION: A clock signal CLK of a duty of 50% on which common mode noise is superimposed and which repeats 1, 0, 1, 0 in synchronism with bit signals is input into a high pass filter 14 and a low pass filter 16, and the common mode noise and a shift voltage V2 are produced. A common mode noise cancellation voltage V3 is generated on the basis of the common mode noise and the shift voltage and is superimposed on the shift voltage V2 to produce a reference voltage Vref.
申请公布号 JP6063805(B2) 申请公布日期 2017.01.18
申请号 JP20130087521 申请日期 2013.04.18
申请人 新日本無線株式会社 发明人 高木 嘉和
分类号 H03M1/08;H03M1/80;H03M1/86 主分类号 H03M1/08
代理机构 代理人
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