发明名称 Tamper-resistant non-volatile memory device
摘要 A non-volatile memory device includes a memory cell array including memory cells, a read circuit that, in operation, obtains pieces of resistance value information each relating to the resistance value of one of the memory cells, an arithmetic circuit that, in operation, calculates a binary reference value based on at least a part of the pieces of resistance value information, and a data adjustment circuit. In operation, the read circuit assigns, based on the binary reference value, 0 or 1 to each of the pieces of resistance value information. In operation, the data adjustment circuit determines whether to adjust the binary reference value, in accordance with a difference between the numbers of pieces of digital data “0” and digital data “1” in the pieces of digital data.
申请公布号 US9548113(B2) 申请公布日期 2017.01.17
申请号 US201514938744 申请日期 2015.11.11
申请人 PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD. 发明人 Yoshimoto Yuhei;Katoh Yoshikazu
分类号 G11C11/00;G11C13/00;G11C16/20 主分类号 G11C11/00
代理机构 McDermott Will & Emery LLP 代理人 McDermott Will & Emery LLP
主权项 1. A non-volatile memory device comprising: a memory cell array including memory cells arranged in an array, each of the memory cells having a resistance value and having a property that the resistance value reversibly transitions among resistance value ranges in a non-volatile manner in a variable state in accordance with application of different electrical signals; a read circuit that, in operation, obtains pieces of resistance value information each relating to the resistance value of one of the memory cells; an arithmetic circuit that, in operation, calculates a binary reference value based on at least a part of the pieces of resistance value information; and a data adjustment circuit, wherein, in operation, the read circuit assigns, based on the binary reference value, 0 or 1 to each of the pieces of resistance value information, thereby generating pieces of digital data including at least one selected from the group consisting of digital data “0” and digital data “1”, and the data adjustment circuit determines whether or not it is necessary to adjust the binary reference value, in accordance with a difference between the number of pieces of the digital data “0” and the number of pieces of the digital data “1” in the pieces of digital data.
地址 Osaka JP