TECHNIQUES FOR INTEGRATION OF GE-RICH P-MOS SOURCE/DRAIN CONTACTS

摘要

Techniques are disclosed for improved integration of germanium (Ge)-rich p-MOS source/drain contacts to, for example, reduce contact resistance. The techniques include depositing the p-type Ge-rich layer directly on a silicon (Si) surface in the contact trench location, because Si surfaces are favorable for deposition of high quality conductive Ge-rich materials. In one example method, the Ge-rich layer is deposited on a surface of the Si substrate in the source/drain contact trench locations, after removing a sacrificial silicon germanium (SiGe) layer previously deposited in the source/drain locations. In another example method, the Ge-rich layer is deposited on a Si cladding layer in the contact trench locations, where the Si cladding layer is deposited on a functional p-type SiGe layer. In some cases, the Ge-rich layer comprises at least 50% Ge (and may contain tin (Sn) and/or Si) and is boron (B) doped at levels above 1E20 cm−3.

主权项

1. A transistor device, comprising:
a substrate having a channel region; a gate electrode above the channel region; and source/drain regions formed on and/or in the substrate and adjacent to the channel region, each of the source/drain regions comprising a p-type germanium (Ge)-rich layer deposited directly on a silicon (Si) surface, wherein the p-type Ge-rich layer comprises at least 50% Ge.