| 摘要 |
PROBLEM TO BE SOLVED: To suppress reliability deterioration of failure diagnosis results.SOLUTION: A control part reads out design information and a result of a delay test to a real chip which are stored in a storage part and the control part selects one analysis target path from each of one or more activated paths Pa, Pb to respective flip flops 10-1 to 10-n (step S1). The control part constructs a deviation calculation model from a deviation between a prediction value when designing delay time caused by the analysis target path and a measurement value in a delay test and calculates probability distribution of prediction values of delay time in which each flip flop is capable of correctly inputting data by using the deviation calculation model (step S2). The control part calculates coincidence between the probability distribution and the measurement result of the delay test (Step S3). The control part changes combination of analysis target paths to be selected and specifies a deviation factor by using the combination of analysis target paths whose coincidence is improved (step S4). |
