Combination of TSV and back side wiring in 3D integration

摘要

The embodiments of the present invention relate generally to the fabrication of integrated circuits, and more particularly to a structure and method for fabricating a 3D integration scheme for multiple semiconductor wafers using an arrangement of intra-wafer through silicon vias (TSVs) to electrically connect the front side of a first integrated circuit (IC) chip to large back side wiring on the back side of the first IC chip and inter-wafer TSVs to electrically connect the first IC chip to a second IC chip.

主权项

1. A method comprising:
forming a first through substrate via (TSV) in a front side of a first substrate, the first TSV having a height less than the total height of the first substrate;
forming a front side wiring layer on the front side of the first substrate to form a first integrated circuit (IC) chip, the front side wiring layer being electrically connected to the first TSV; forming a first bonding layer over the front side wiring layer; bonding the first IC chip to a second IC chip, the bond formed between the first bonding layer of the first IC chip and a second bonding layer of the second IC chip; removing a portion of a back side of the first substrate to expose a lower portion of the first TSV using a combination of hydrofluoric/nitric/acetic acid etching and reactive ion etching, the back side of the first substrate being opposite the front side;
forming a back side wiring layer on the back side of the first substrate, the back side wiring layer being electrically connected to the first TSV, wherein the back side wiring layer is formed such that it has a thickness that is eight to ten times a thickness of the front side wiring layer; andforming a second TSV and a third TSV, the second TSV and third TSV each extending from the front side of the first substrate through an entire thickness of the back side wiring layer, the first IC chip, the first bonding layer, the second bonding layer, and the second IC chip, such that the top surface and the bottom surface of the second TSV and third TSV are exposed, and wherein the top surface of the second TSV and the top surface of the third TSV are coplanar with the front side of the first substrate, and wherein the bottom surface of the second TSV and the bottom surface of the third TSV are coplanar with the back side wiring layer, the second TSV providing an electrical connection between the second IC chip and the back side wiring layer of the first IC chip, and wherein the second TSV and the third TSV are each disposed at a periphery of the first IC chip and the second IC chip.