| 主权项 |
1. A system-level packaging method, comprising:
providing a packaging substrate having a first functional surface and a second surface with wiring arrangement within the packaging substrate and between the first functional surface and the second surface; forming at least two package layers on the first functional surface of the packaging substrate, wherein the at least two package layers include a first package layer formed by:
attaching at least one first chip group and at least one first passive device group spaced apart on the packaging substrate by a glue layer, the at least one first chip group and the at least one first passive device group comprise connection parts having a first thickness,after the at least one chip group and the at least one passive device group is attached on the packaging substrate, forming a first sealant layer on the packaging substrate covering the at least one first chip group and the at least one first passive device group, and filling spaces between the at least one first chip group and the at least one first passive device group, the first sealant layer has a second thickness directly above the at least one first chip group and the at least one first passive device group, wherein the first thickness and the second thickness are equal, wherein the connection parts of the at least one first chip group and the at least one first passive device group are exposed from the first sealant layer, the at least one first chip group and the at least one first passive device group are insulated from each other, and a top surface of the first sealant layer is coplanar with the top surface of the connection parts of the at least one first chip group and the at least one first passive device group, andafter forming the first sealant layer on the packaging substrate, forming vias through the first sealant layer and extending to the packaging substrate, and forming a first wiring layer passing through the vias in the first sealant layer and electrically connects to the packaging substrate, the first wiring layer providing electrical connection between the at least one first chip group and the at least one first passive device group in the first mounting layer; stacking at least one second chip group and at least one second passive device group directly on the first wiring layer; forming a top sealant layer; and planting connection balls on the second functional surface of the packaging substrate. |
