发明名称 Production of spacers at flanks of a transistor gate
摘要 The production of spacers at flanks of a transistor gate, including a step of forming a dielectric layer covering the gate and a peripheral region of a layer of semiconductor material surrounding the gate, including forming a superficial layer covering the gate and the peripheral region; partially removing the superficial layer configured so as to completely remove the superficial layer at the peripheral region while preserving a residual part of the superficial layer at the flanks; and selective etching of the dielectric layer vis-à-vis the material of the residual part of the superficial layer and vis-à-vis the semiconductor material.
申请公布号 US9543409(B2) 申请公布日期 2017.01.10
申请号 US201514855834 申请日期 2015.09.16
申请人 COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES;STMICROELECTRONICS SA;STMICROELECTRONICS (Crolles 2) SAS 发明人 Arvet Christian;Barnola Sebastien;Lagrasta Sebastien;Posseme Nicolas
分类号 H01L29/66;H01L21/283;H01L21/311;H01L29/423;H01L29/51 主分类号 H01L29/66
代理机构 Oblon, McClelland, Maier & Neustadt, L.L.P. 代理人 Oblon, McClelland, Maier & Neustadt, L.L.P.
主权项 1. A method for producing spacers at flanks of a transistor gate, the gate being situated above a layer of a semiconductor material, the method comprising successively the following steps: forming a dielectric layer that covers the gate and at least a peripheral region of the layer of semiconductor material surrounding the gate; anisotropic etching of the dielectric layer, thereby reducing a thickness of the dielectric layer at a region covering an upper surface of the gate and at the peripheral region, while substantially preserving a thickness of the dielectric layer at the flanks; forming a superficial layer covering the dielectric layer; partial etching of the superficial layer configured so as to completely remove the superficial layer at the peripheral region while preserving a residual part of the superficial layer at the flanks, and while at least partly preserving the dielectric layer at the peripheral region; and then, after the partial etching, selectively etching the dielectric layer with respect to the residual part of the superficial layer and with respect to the layer of semiconductor material.
地址 Paris FR