Error detection on a low pin count bus

摘要

Systems and methods that implement communication of error information on a bus, including a bus having a small number of pins are disclosed. In one embodiment, an apparatus includes an interface circuit configured to couple to a bus and one or more sideband signals. The sideband signals may be used to communicate error information such as parity information for a bus that does not otherwise have this capability. In some embodiments, parity information may be driven on the bus during a portion of a bus transaction corresponding to unused address bits.

主权项

1. An apparatus, comprising:
a communication bridge device including a bus interface circuit configured to couple to a service processor via a serial bus and first and second sideband signal lines for the serial bus, wherein the serial bus is a low pin count bus that has less than 10 signal lines, wherein the serial bus includes a set of address/data signal lines, a clock signal line, a reset signal line, and a cycle delimiter signal line, and wherein the serial bus is compatible with an Industry Standard Architecture (ISA) bus; wherein the bus interface circuit is further configured to use the first and second sideband signal lines to communicate error information in response to detecting an error condition on the serial bus, wherein the bus interface circuit is configured to communicate parity error information on the first and second sideband signal lines in response to detecting a parity error condition on the serial bus; and wherein the communication bridge device is configured to convey at least a portion of the parity error information during an addressing portion of a response to a bus transaction corresponding to address bits that are unused by the response to the bus transaction.