Conditional operation in an internal processor of a memory device

摘要

An internal processor of a memory device configured to selectively execute instructions in parallel. One such internal processor includes a plurality of arithmetic logic units (ALUs), each connected to conditional masking logic, and each configured to process conditional instructions. A condition instruction may be received by a sequencer of the memory device. Once the condition instruction is received, the sequencer may enable the conditional masking logic of the ALUs. The sequencer may toggle a signal to the conditional masking logic such that the masking logic masks certain instructions if a condition of the condition instruction has been met, and masks other instructions if the condition has not been met. In one embodiment, each ALU in the internal processor may selectively perform instructions in parallel.

主权项

1. A memory device comprising:
a sequencer configured to receive a condition instruction, selectively generate a first signal, and selectively generate a second signal having a value indicating whether a condition of the condition instruction has been met; and an internal processor coupled to the sequencer, wherein the internal processor comprises a plurality of arithmetic logic unit (ALU) blocks configured to operate in parallel, each ALU block being configured to selectively execute operations based on an output of a conditional masking logic of the internal processor, wherein the sequencer controls the output of the conditional masking logic via the selectively generated first signal and second signal, wherein each ALU block of the plurality of ALU blocks comprises a counter to count a number of first conditional instructions and then a number of second conditional instructions; wherein the memory device is a processor-in-memory or a multi-chip package device.