Using a decrementer interrupt to start long-running hardware operations before the end of a shared processor dispatch cycle

摘要

Systems, methods, and computer program products to perform an operation, the operation comprising processing a first logical partition on a shared processor for the duration of a dispatch cycle, issuing, by a hypervisor, at a predefined time prior to completion of the dispatch cycle, a lightweight hypervisor decrementer (HDEC) interrupt specifying a cache line address buffer location in a virtual processor, and responsive to the lightweight HDEC, writing, by the shared processor, a set of cache line addresses used by the first logical partition to the cache line address buffer location in the virtual processor.

主权项

1. A system comprising:
one or more shared computer processors; and a memory containing a program, which when executed by the one or more shared computer processors, performs an operation comprising:
processing a plurality of logical partitions on a shared processor for the duration of a respective dispatch cycle;issuing, by a hypervisor, at a predefined time prior to completion of each dispatch cycle, a lightweight hypervisor decrementer (HDEC) interrupt specifying a respective cache line address buffer location in a virtual processor;responsive to each lightweight HDEC interrupt, writing, by the shared processor, a set of cache line addresses used by each logical partition to the respective cache line address buffer location in the virtual processor;determining an average amount of time required to write the sets of cache line addresses; andsetting the average amount of time as the predefined time to issue the lightweight HDEC during subsequent processing of each logical partition.