发明名称 CHIP PACKAGE STRUCTURE AND METHOD FOR FORMING CHIP PACKAGE
摘要 The present disclosure relates to a chip package structure and a method for forming a chip package. A package unit is formed from the chip and an encapsulant surrounding the chip to have an increased area. A redistribution layer is formed on the package unit to draw out to and redistribute input/output terminals on a surface of the chip. The redistribution layer is then electrically coupled to a leadframe or a printed circuit board by external and electrical connectors. The method and the package structure are suitable for providing a chip package having input/output terminals with high density, reducing package cost, and improving package reliability.
申请公布号 US2016351483(A1) 申请公布日期 2016.12.01
申请号 US201615167215 申请日期 2016.05.27
申请人 Silergy Semiconductor Technology (Hangzhou) Ltd. 发明人 Ye Jiaming
分类号 H01L23/495;H01L23/31;H01L23/00;H01L21/48;H01L21/56;H01L21/78 主分类号 H01L23/495
代理机构 代理人
主权项 1. A method for forming a chip package, comprising: singulating a plurality of chips from a wafer, wherein each of said plurality of chips is provided with a plurality of pads of input/output terminals on an active surface; attaching said plurality of chips to a plate with active surfaces facing upward; filling spaces between adjacent ones of said plurality of chips with an encapsulant by a molding process, so that each of said plurality of chips and said encapsulant surrounding it form a package unit; forming an insulating layer having openings on said package unit, wherein each of said openings at least exposes a portion of each of said plurality of pads; forming a redistribution layer on said insulating layer which contacts exposed portion of each of said plurality of pads to redistribute said input/output terminals; and electrically coupling said redistribution layer to a leadframe or a printed circuit board by external and electrical connectors.
地址 Hangzhou CN
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