发明名称 ジッタモニタ回路
摘要 A jitter monitor includes: a voltage generating circuit configured to generate a first voltage that is varied with time at a predetermined inclination; a voltage reducing circuit configured to reduce the first voltage by a predetermined voltage in synchronization with a first clock signal so as to generate a second voltage that is varied with time at the predetermined inclination in synchronization with the first clock signal; and a sampling circuit configured to sample a portion having the predetermined inclination of the second voltage.
申请公布号 JP6036330(B2) 申请公布日期 2016.11.30
申请号 JP20130009518 申请日期 2013.01.22
申请人 富士通株式会社 发明人 田村 泰孝
分类号 H04L25/02 主分类号 H04L25/02
代理机构 代理人
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