发明名称 可変インダクタ回路及び高周波回路
摘要 A first transistor (Trl ,Tr5) and a second transistor (Tr2,Tr4) cascade-connected, a wiring (lnl,ln2) which connects a drain of the first transistor and a gate of the second transistor, a capacitor (C1) whose one terminal is connected between the first transistor and the second transistor cascade-connected and whose other terminal is grounded, and a control circuit (2, 2a, 30, 40) are included in a variable inductor circuit. A control circuit adjusts the inductance value of said variable inductor by controlling a capacitance value of the capacitor or gate voltage of the first transistor or the second transistor.
申请公布号 JP6036564(B2) 申请公布日期 2016.11.30
申请号 JP20130125291 申请日期 2013.06.14
申请人 富士通株式会社 发明人 佐藤 優
分类号 H03H11/48;H03F3/193 主分类号 H03H11/48
代理机构 代理人
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