| 摘要 |
A first less power consuming processing core PU1 controls a display DISP via first display interface in phase 430. A second more power consuming processing core PU2 also controls display DISP via a second display interface in phase 410. After a trigger in phase 420, the first core PU1 causes the second core PU2 to enter or leave hibernation 450 in phases 440 and 470, respectively. The second core leaves hibernation if a graphic mode unsupported by the first processor is requested or its communications capabilities are required. Hibernation is entered if reduce map view graphics is required. Context is stored upon transition into hibernation. Both cores can be interfaced with a shared random access memory. Hibernation state is generated by setting the clock frequency to zero. Intermediate low power states allowing faster transitions to an active state are disclosed. Used for conserving battery power in embedded devices, e.g. smartphones. |
