| 摘要 |
An apparatus comprising circuitry implementing units comprises: a pipelined execution unit 50 configurable to operate in either a first mode in which an odd number of pipeline stages 57 are required to produce each intermediate execution result 65 during execution of a multipass or iterative algorithm, or a second mode in which an even number of pipeline stages 58 are required to produce each intermediate execution result, and the even number is greater than the odd number; and a controller configured for switching the operation between the first mode and the second mode to avoid a conflict with either a further iteration of a value currently in progress or introduction of a new calculation into the pipelined execution unit, where the controller is operable to configure the pipelined execution unit to reduce latency when the pipeline is not saturated by operating in the first mode and to increase throughput when the pipeline is saturated for a particular type of instruction by operating in the second mode, until the pipeline is not saturated. |
