Three-Dimensional Vertical Memory Comprising Dice with Different Interconnect Levels

摘要

The present invention discloses a three-dimensional vertical memory (3D-MV). It comprises at least a 3D-array die and at least a peripheral-circuit die. The 3D-array die comprises a plurality of vertical memory strings. The number of interconnect levels in the peripheral-circuit die is more than the number of interconnect levels in the 3D-array die, but substantially less than the number of memory cells on each of the vertical memory strings in the 3D-array die.

主权项

1. A three-dimensional vertical memory (3D-MV), comprising:
a 3D-array die comprising at least a 3D-MV array, wherein said 3D-MV array comprises a plurality of vertical memory strings, each of said vertical memory strings comprising a plurality of vertically stacked memory cells; a peripheral-circuit die comprising at least an off-die peripheral-circuit component of said 3D-MV array, wherein said off-die peripheral-circuit component is absent from said 3D-array die; means for coupling said 3D-array die and said peripheral-circuit die; wherein the number of interconnect levels in said peripheral-circuit die is more than the number of interconnect levels in said 3D-array die, but substantially less than the number of memory cells on each of said vertical memory strings in said 3D-array die; and, said 3D-array die and said peripheral-circuit die are separate dice.