| 主权项 |
1. A display device, comprising:
a display panel; and a display driver driving the display panel, wherein the display driver is connected to a host with a clock lane and at least one data lane, wherein the display driver comprises:
an interface circuit configured to receive an external clock signal from the host via the clock lane, receive a data signal from the host via the data lane, and output reception data transmitted over the data signal;a control circuit configured to output an internal clock signal synchronous with the external clock signal; anddrive circuitry configured to drive the display panel in response to image data included in the reception data in synchronization with the internal clock signal outputted by the control circuit, wherein, when the clock lane and the data lane are set to a first mode, the interface circuit is configured to perform a clock recovery on the data signal transmitted over the data lane and generate the reception data by sampling the data signal in synchronization with a recovered clock signal obtained by the clock recovery, wherein, when the clock lane and the data lane are set to a second mode, the interface circuit is configured to generate the reception data by sampling the data signal in synchronization with the external clock signal transmitted over the clock lane, and wherein the control circuit is configured to output the internal clock signal in response to a type of a reception packet included in the reception data when the clock lane and the data lane are set to the second mode. |
