SYSTEM AND METHOD FOR POWER VERIFICATION USING EFFICIENT MERGING OF POWER STATE TABLES

摘要

A power verification system requires a combination of design and its power intent. A power intent (PI) input specifies the power architecture of a design through specification of power/voltage domains, their corresponding power supplies and a collection of power management devices. Power state tables (PSTs) specified in PI capture the legal combinations of power states (voltage values) for the various sets of supply nets or supply ports of a design. A power verification system requires determining the power supply relationships of voltage/power domains which requires merging of PSTs. The system described efficiently merges PSTs by iteratively selecting only a subset of PSTs that are relevant to the supply pair of interest, that are pruned initially and as the merge progresses. This provides orders of magnitude speedup and resource reduction. A user interface allows display of identified power verification failures and may include an input device for facilitating correction of at least one of the electronic circuit design and the power intent file.

主权项

1. A method implemented for a power verification tool in a computing system for constructing power state tables in a verification of power implementation of an electronic circuit design, the method comprising:
receiving a description of at least a portion of an electronic circuit design having two or more power domains, and storing the received description in a storage medium accessible to a processor; receiving and storing in the storage medium a power intent file that specifies a power architecture of power/voltage domains, their power supplies and any corresponding power devices of the electronic circuit design; preparing, by the processor, to construct overall power state tables by removing any inconsistent power states from power state tables embedded in the power intent file; constructing, by the processor, overall and relevant power state tables by selectively merging those power state tables that identify a relationship between power supplies of interest; and displaying on a computer display identified power verification failures and using an input device to facilitate correction and storage of at least one of the electronic circuit design and the power intent file.