发明名称 演算処理装置及び演算処理方法
摘要 In a processor that includes a plurality of multipliers and a plurality of adders to execute matrix product processing, each data of input vector data involved in the arithmetic processing is used in two multipliers, whereby arithmetic processing of elements in different rows and different columns in a matrix product operation is executed with a single instruction, that enables the sharing of input data to reduce the number of times data are moved in the whole matrix product processing and reduce power consumption.
申请公布号 JP6003744(B2) 申请公布日期 2016.10.05
申请号 JP20130060018 申请日期 2013.03.22
申请人 富士通株式会社 发明人 安島 雄一郎
分类号 G06F17/16;G06F15/80 主分类号 G06F17/16
代理机构 代理人
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