| 摘要 |
In an example, a linear feedback shift register (LFSR) provides pseudorandom bit sequences (PRBSs) to an interconnect for training, testing, and scrambling purposes. The interconnect may include a state machine, with states including LOOPBACK, CENTERING, RECENTERING, and ACTIVE states, among others The interconnect is permitted to move from "CENTERING" to "LOOPBACK" via a sideband signal. In LOOPBACK, CENTERING, and RECENTERING, PRBSs are used for training and testing purposes to electrically characterize and test the interconnect, and to locate a midpoint for a reference voltage V ref. A unique, noncorrelated PRBS is provided to each lane, calculated using one common output bit. Multiple bits per lane may also be computed per clock cycle so that the LFSR can run at a slower clock rate than the interconnect. A selecting network may also be provided so that, as necessary, "victim," "aggressor," and "neutral" lanes may be provided for testing purposes. |
