| 主权项 |
1. A direct memory access (DMA) controller controlling DMA transfer, comprising:
a plurality of transfer request generating units, each of the transfer request generating units notifying a scheduler of a transfer request based on transfer request setting information including at least a transfer setting number and a transfer activation condition set thereto; the scheduler receiving the transfer requests from the plurality of transfer request generating units, scheduling the received transfer requests based on priority setting information set in advance, selecting one transfer setting number corresponding to a transfer setting commanded by the transfer request serving as an execution target based on a scheduling result, and notifying a DMA transfer executing unit of the selected transfer setting number; and the DMA transfer executing unit receiving the notified transfer setting number from the scheduler, reading transfer setting information corresponding to the received transfer setting number from a plurality of pieces of transfer setting information set in advance, and executing the DMA transfer, wherein the transfer request setting information includes a preceding standby time, the transfer request generating unit notifies the scheduler of a standby request before the transfer request based on the preceding standby time, and the scheduler receives the standby request, and gives a standby notification to the DMA transfer executing unit based on the priority setting information set in advance. |
