发明名称 情報処理装置、遅延差測定方法、及び遅延差測定プログラム
摘要 Each of the plurality of second processing units (20A, 20B) includes: a counter (22A, 22B) that counts a count value in synchronization with such a counter included in each remaining second processing unit; a register (23A, 23B) that holds the count value of the counter (22A, 22B); and a control unit (24A, 24B) that stores the count value, which is counted by the counter (22A, 22B) when receiving a measurement instruction from the first processing unit (10), as a receipt-timing count value into the register (23A, 23B) and notifies the first processing unit (10) of the held receipt-timing count value, and the first processing unit (10) calculates one or more differences between a plurality of the receipt-timing count values notified from the second processing units (20A, 20B) as a transmitting delay difference from the first processing unit (10) to each of the plurality of second processing units (20A, 20B).
申请公布号 JP5970958(B2) 申请公布日期 2016.08.17
申请号 JP20120116146 申请日期 2012.05.22
申请人 富士通株式会社 发明人 竹原 勝
分类号 H04L7/00 主分类号 H04L7/00
代理机构 代理人
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