| 摘要 |
According to one embodiment, a method includes generating a first clock signal and a second clock signal with non-overlapping clock phases. The method may further include latching, by a plurality of master latches of a shift register, a plurality of values at a plurality of inputs of the master latches in response to a particular type of logical transition of the first clock signal. The method also includes latching, by a plurality of slave latches of the shift register, a plurality of output values of the plurality of master latches at a plurality of inputs of the slave latches in response to a particular type of logical transition of the second clock signal. |
