| 摘要 |
Various embodiments generally relate to techniques for cooperation between a higher function core and a lower power core to minimize effects of interrupts on a present flow of execution of instructions. An apparatus includes the lower power core and the higher function core. The lower power core includes a first instruction pipeline, and the lower power core stops a first flow of execution in the first instruction pipeline and executes instructions of a handler routine in the first instruction pipeline to perform a first task of handling an interrupt. The higher function core includes a second instruction pipeline, and the higher function core schedules, after performing the first task, execution of instructions of a second task of handling the interrupt in the second instruction pipeline to follow a second flow of execution in the second instruction pipeline. The first task is more time-sensitive than the second task. Other embodiments are described and claimed. |
