Memory System Topologies Including A Buffer Device And An Integrated Circuit Memory Device

摘要

Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device. The buffer device segments and merges the data transferred between the memory controller that expects a particular memory organization and actual memory organization.

主权项

1. A plurality of coupled devices comprising:
a plurality of integrated circuit devices, each integrated circuit device of the plurality of integrated circuit devices having a memory array to store data; an integrated circuit device having a memory array, wherein the integrated circuit device is operable as a memory device, the integrated circuit device including
a first interface to receive control information, anda second interface to output control signals to at least one integrated circuit device of the plurality of integrated circuit devices in response to the control information; a first signal path coupled to the second interface and the plurality of integrated circuit devices, the first signal path to convey the data, associated with the control signals, between the second interface and the plurality of integrated circuit devices; and a second signal path coupled to the second interface and the plurality of integrated circuit devices, the second signal path to convey the control signals from the second interface to the plurality of integrated circuit devices.