| 发明名称 |
HARDWARE APPARATUSES AND METHODS RELATING TO ELEMENTAL REGISTER ACCESSES |
| 摘要 |
Methods and apparatuses relating to a vector instruction with a register operand with an elemental offset are described. In one embodiment, a hardware processor includes a decode unit to decode a vector instruction with a register operand with an elemental offset to access a first number of elements in a register specified by the register operand, wherein the first number is a total number of elements in the register minus the elemental offset, access a second number of elements in a next logical register, wherein the second number is the elemental offset, and combine the first number of elements and the second number of elements as a data vector, and an execution unit to execute the vector instruction on the data vector. |
| 申请公布号 |
US2016188334(A1) |
申请公布日期 |
2016.06.30 |
| 申请号 |
US201414582784 |
申请日期 |
2014.12.24 |
| 申请人 |
Intel Corporation |
发明人 |
Lee Victor;Echeruo Ugonna;Chrysos George;Mellempudi Naveen |
| 分类号 |
G06F9/30 |
主分类号 |
G06F9/30 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A hardware processor comprising:
a decode unit to decode a vector instruction with a register operand with an elemental offset to:
access a first number of elements in a register specified by the register operand, wherein the first number is a total number of elements in the register minus the elemental offset;access a second number of elements in a next register, wherein the second number is the elemental offset; andcombine the first number of elements and the second number of elements as a data vector; and an execution unit to execute the vector instruction on the data vector. |
| 地址 |
Santa Clara CA US |
