| 摘要 |
Managing allocation of physical registers in a block-based instruction set architecture (ISA), and related apparatuses and methods, are disclosed. In one aspect, an apparatus provides an instruction processing circuit communicatively coupled to multiple physical registers. The instruction processing circuit includes a register rename map that comprises an association between at least one architectural register and at least one of the multiple physical registers. The instruction processing circuit further comprises an in-use indicator set associated with the register rename map, the in-use indicator set indicative of an in-use physical register among the multiple physical registers. The instruction processing circuit is configured to copy the in-use indicator set to an output in-use indicator set, and modify the output in-use indicator set upon detection of a block-based write instruction to mark the in-use physical register as unused. |
