发明名称 |
TEST CIRCUIT AND METHOD OF CONTROLLING TEST CIRCUIT |
摘要 |
A test circuit, provided to a semiconductor device including a plurality of semiconductor chips, includes: a test clock terminal provided to a first chip; a plurality of clock paths disposed between the first chip and a second chip through which the test clock is transmitted from the first chip to the second chip; a test unit provided to the second chip for testing the second chip by using the test clock transmitted to the second chip; a clock detection unit provided to the second chip, and detects the test clock that is received through each of the plurality of clock paths; and a clock path selection unit which is provided to the second chip, selects a first clock path among the plurality of clock paths as a test clock path, and supplies the test clock transmitted through the test clock path to the test unit. |
申请公布号 |
EP3037833(A2) |
申请公布日期 |
2016.06.29 |
申请号 |
EP20150192467 |
申请日期 |
2015.10.30 |
申请人 |
FUJITSU LIMITED |
发明人 |
OSHIYAMA, GEN;MORIYAMA, OSAMU;SHIKIBU, TAKAHIRO;CHIYONOBU, AKIHIRO;YAMAZAKI, IWAO |
分类号 |
G01R31/3185;G01R31/317 |
主分类号 |
G01R31/3185 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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