发明名称 電子機器、通信制御方法、及びプログラム
摘要 PROBLEM TO BE SOLVED: To bring out maximum processing capacity of a CPU without a separately prepared oscillation circuit dedicated to communication or restriction of a baud rate for serial communication.SOLUTION: An electronic apparatus 1 comprises: a communication module 10 for performing communication with a communication partner at a predetermined communication speed; a PLL 22 for changing a frequency of an operation clock of a CPU core 21 according to a processing load; the CPU core 21 for determining whether the changed frequency of the operation clock is a frequency in which a communication error occurs; and a transmission/reception control unit 242 for operating with the same operation clock as that of the CPU core 21. When it is determined that the frequency is the one in which a communication error occurs, the communication module 10 and the transmission/reception control unit 242 performs correction of a bit array for transmission data to be transmitted/received and reconstruction of receiving data on the basis of a difference between both operation clocks.
申请公布号 JP5942702(B2) 申请公布日期 2016.06.29
申请号 JP20120187450 申请日期 2012.08.28
申请人 カシオ計算機株式会社 发明人 遠田 尚登
分类号 G06F1/12;H04L29/06 主分类号 G06F1/12
代理机构 代理人
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