| 主权项 |
1. A random access memory integrated circuit responsive to an externally supplied clock input, the random access memory integrated circuit comprising:
a dynamic memory array configured in one or more banks, wherein the dynamic memory array requires periodic refreshing to maintain data; and one or more refresh control circuits generating refresh requests inside the random access memory integrated circuit, the dynamic memory array configured to receive read and write access requests, wherein the read or write access requests have priority over pending refresh requests, wherein one pending refresh request to one of the banks is retired on any clock cycle not requiring an access of that bank, the refresh completing in the clock cycle, the read access requests initiating an access to the dynamic memory array without first determining whether data is available from outside the dynamic memory array, thereby avoiding a delay associated with such determination. |
