Processor with Polymorphic Instruction Set Architecture

摘要

The present disclosure provides a processor having polymorphic instruction set architecture. The processor comprises a scalar processing unit, at least one polymorphic instruction processing unit, at least one multi-granularity parallel memory and a DMA controller. The polymorphic instruction processing unit comprises at least one functional unit. The polymorphic instruction processing unit is configured to interpret and execute a polymorphic instruction and the functional unit is configured to perform specific data operation tasks. The scalar processing unit is configured to invoke the polymorphic instruction and inquire an execution state of the polymorphic instruction. The DMA controller is configured to transmit configuration information for the polymorphic instruction and transmit data required by the polymorphic instruction to the multi-granularity parallel memory. With the present disclosure, programmers can redefine a processor instruction set based on algorithm characteristics of applications after tape-out of a processor.

主权项

1. A processor having polymorphic instruction set architecture, comprising a scalar processing unit, at least one polymorphic instruction processing unit, at least one multi-granularity parallel memory and a DMA controller, the polymorphic instruction processing unit comprising at least one functional unit, wherein:
the polymorphic instruction processing unit is configured to interpret and execute a polymorphic instruction and the functional unit is configured to perform specific data operation tasks, the polymorphic instruction being a sequence of a plurality of microcode records to be executed successively, the microcode records indicating actions to be performed by the respective functional units within a particular clock period; the scalar processing unit is configured to invoke the polymorphic instruction and inquire an execution state of the polymorphic instruction; and the DMA controller is configured to transmit configuration information for the polymorphic instruction and transmit data required by the polymorphic instruction to the multi-granularity parallel memory.