SRAM READ BUFFER WITH REDUCED SENSING DELAY AND IMPROVED SENSING MARGIN

摘要

A device includes a static random access memory (SRAM) cell and a read buffer coupled to an output of the SRAM cell. The read buffer includes an inverter and a switch. An input of the inverter is responsive to the output of the SRAM cell. A control terminal of the switch is responsive to an output of the inverter.