发明名称 |
POSTED INTERRUPT ARCHITECTURE |
摘要 |
An interrupt is identified from an input/output (I/O) device and an address of a particular cache line is identified associated with the interrupt. The cache line corresponds to a destination of the interrupt and represents one or more attributes of the interrupt. A request is sent to a coherency agent to acquire ownership of the particular cache line and a request is sent to perform a read-modify-write (RMW) operation on the cache line based on the interrupt. |
申请公布号 |
WO2016085645(A1) |
申请公布日期 |
2016.06.02 |
申请号 |
WO2015US59821 |
申请日期 |
2015.11.10 |
申请人 |
INTEL CORPORATION |
发明人 |
GUDDETI, JAYAKRISHNA;CHANG, LUKE;SANKARAN, RAJESH M.;THALIYIL, JUNAID F. |
分类号 |
G06F13/42;G06F11/16;G06F13/24 |
主分类号 |
G06F13/42 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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