Dynamic memory utilization in a system on a chip

摘要

Various embodiments of methods and systems for dynamically managing the capacity utilization of a memory component in a system on a chip (“SoC”) are disclosed. Memory utilization is optimized in certain embodiments through dynamic compression and decompression within a memory subsystem. Based on parameters of the SoC that are indicative of a quality of service (“QoS”) level, a memory controller may determine that the format of the data in a write request should be converted and stored in a relinked memory address. Subsequently, a primary memory address associated with the data may be released for storage of different data. Similarly, embodiments may return data requested in a write request in a format different than that which was requested.

主权项

1. A method for dynamically managing the capacity utilization of a memory component in a system on a chip (“SoC”), the method comprising:
monitoring one or more parameters of the SoC that are indicative of a quality of service (“QoS”) level; receiving at a memory controller comprised within a memory subsystem a first transaction request transmitted over a bus from a first master component, wherein the first transaction request is a write request; determining a primary memory address for data associated with the first transaction request, wherein the primary memory address is located within a first data bank of the memory component; determining a format of the data associated with the first transaction request; based on the one or more monitored parameters, determining to convert the format of the data associated with the first transaction request; storing the data in its converted format at a relinked memory address, wherein the relinked memory address is located within a second data bank of the memory component; and releasing the primary memory address for storage of data associated with a subsequent transaction request.