发明名称 Memory receiver circuit for use with memory of different characteristics
摘要 Embodiments include systems, methods, and apparatuses for reading a data signal from a memory, such as a dynamic random access memory (DRAM). In one embodiment, a memory receiver may include a differential amplifier to receive a data signal from the memory and pass a differential output signal based on a voltage difference between the data signal and a reference voltage. The data signal may have a first direct current (DC) average voltage level, and the differential amplifier may shift the differential output signal to a second DC average voltage level that is substantially constant over a range of values of the first DC average voltage level. In another embodiment, a voltage offset compensation (VOC) circuit may apply a compensation voltage to the output signal that is based on an activated rank or an identity of the memory module. Other embodiments may be described and claimed.
申请公布号 US9355693(B2) 申请公布日期 2016.05.31
申请号 US201313830637 申请日期 2013.03.14
申请人 Intel Corporation 发明人 Maeng Moonkyun;Martin Aaron;Chuang Hsiao-Ching
分类号 G11C7/06;G11C7/10;G11C5/14;G11C16/28 主分类号 G11C7/06
代理机构 Schwabe, Williamson & Wyatt, P.C. 代理人 Schwabe, Williamson & Wyatt, P.C.
主权项 1. An apparatus comprising: a differential amplifier coupled to a positive supply rail to receive a positive supply voltage (Vcc) and including circuitry to: receive a data signal at an input terminal of the differential amplifier from a memory, the data signal having a first direct current (DC) average voltage level, wherein the data signal changes between a first voltage level to represent a first logical value and a second voltage level to represent a second logical value, and the first DC average voltage level is an average voltage of the first voltage level and the second voltage level;pass a differential output signal at a pair of output terminals of the differential amplifier based on a voltage difference between the data signal and a reference voltage; andshift the differential output signal to a second DC average voltage level, wherein the second DC average voltage level is substantially constant over a range of voltages of the first DC average voltage level, and wherein the second DC average voltage level is an average voltage of a third voltage level representing the first logical value and a fourth voltage level representing the second logical value.
地址 Santa Clara CA US