| 发明名称 | Semiconductor memory device and data erasing method | ||
| 摘要 | A semiconductor memory device includes a memory cell array including a plurality of groups of memory cells above a substrate, the groups including a first group and a second group, each of the first and second groups including a first memory string and a second memory string, the first memory string including first memory cells that are disposed in a first layer, the second memory string including second memory cell that are disposed in a second layer above the first layer, and a controller configured to perform an erasing operation on the memory cells, the erasing operation including a verifying operation on the memory cells to determine on a layer by layer basis whether the memory cells failed to erase data stored therein. | ||
| 申请公布号 | US9355731(B2) | 申请公布日期 | 2016.05.31 |
| 申请号 | US201514637292 | 申请日期 | 2015.03.03 |
| 申请人 | Kabushiki Kaisha Toshiba | 发明人 | Shiga Hidehiro;Shirakawa Masanobu;Abe Kenichi |
| 分类号 | G11C16/14;G11C16/04;G11C16/34;G11C16/16 | 主分类号 | G11C16/14 |
| 代理机构 | Patterson & Sheridan, LLP | 代理人 | Patterson & Sheridan, LLP |
| 主权项 | 1. A semiconductor memory device comprising: a memory cell array including a plurality of groups of memory cells above a substrate, the groups including a first group and a second group, each of the first and second groups including a first memory string and a second memory string, the first memory string including first memory cells that are disposed in a first layer, the second memory string including second memory cells that are disposed in a second layer above the first layer; and a controller configured to perform an erasing operation on the memory cells, the erasing operation including a verifying operation on the memory cells to determine on a layer by layer basis whether the memory cells failed to erase data stored therein. | ||
| 地址 | Tokyo JP | ||