| 发明名称 |
DESIGN STRUCTURE FOR MICROPROCESSOR ARITHMETIC LOGIC UNITS |
| 摘要 |
A method in a computer-aided design system for generating a functional design model of a processor, is described herein. The method comprises generating a functional representation of logic to determine whether an instruction is an updating instruction or a non-updating instruction. The method further comprises generating a functional representation of a first arithmetic logic unit (ALU) coupled to a general register in the processor, the first ALU to execute the instruction if the instruction is an updating instruction and store an update value in the general register, and generating a functional representation of a second ALU in the processor to execute the instruction if the instruction is a non-updating instruction. |
| 申请公布号 |
US2016147531(A1) |
申请公布日期 |
2016.05.26 |
| 申请号 |
US201514865555 |
申请日期 |
2015.09.25 |
| 申请人 |
International Business Machines Corporation |
发明人 |
Ayzenfeld Avraham;Eisen Lee E.;Curran Brian W.;Jacobi Christian |
| 分类号 |
G06F9/30 |
主分类号 |
G06F9/30 |
| 代理机构 |
|
代理人 |
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| 主权项 |
1. A method in a computer-aided design system for generating a functional design model of a processor, said method comprising:
generating a functional representation of logic to determine whether an instruction is an updating instruction or a non-updating instruction; generating a functional representation of a first arithmetic logic unit (ALU) coupled to a general register in the processor, the first ALU to execute the instruction if the instruction is an updating instruction and store an update value in the general register; and generating a functional representation of a second ALU in the processor to execute the instruction if the instruction is a non-updating instruction. |
| 地址 |
Armonk NY US |
