发明名称 |
SEMICONDUCTOR DEVICE INCLUDING A SUPERLATTICE AND REPLACEMENT METAL GATE STRUCTURE AND RELATED METHODS |
摘要 |
A semiconductor device may include a substrate having a channel recess therein, a plurality of spaced apart shallow trench isolation (STI) regions in the substrate, and source and drain regions spaced apart in the substrate and between a pair of the STI regions. A superlattice channel may be in the channel recess of the substrate and extend between the source and drain regions, with the superlattice channel including a plurality of stacked group of layers, and each group of layers of the superlattice channel including stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A replacement gate may be over the superlattice channel. |
申请公布号 |
US2016149023(A1) |
申请公布日期 |
2016.05.26 |
申请号 |
US201514948547 |
申请日期 |
2015.11.23 |
申请人 |
MEARS TECHNOLOGIES, INC. |
发明人 |
Mears Robert J.;King LIU Tsu-Jae;Takeuchi Hideki |
分类号 |
H01L29/778;H01L29/66;H01L29/06;H01L29/15 |
主分类号 |
H01L29/778 |
代理机构 |
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代理人 |
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主权项 |
1. A method for making a semiconductor device comprising:
forming a plurality of spaced apart shallow trench isolation (STI) regions in a substrate; forming a dummy gate on the substrate between a pair of the STI regions; forming source and drain regions in the substrate on opposing sides of the dummy gate and between the pair of STI regions; forming a dielectric layer on the substrate surrounding the dummy gate; removing the dummy gate and portions of the substrate beneath the dummy gate to define a channel recess in the substrate between the source and drain regions; forming a superlattice channel in the channel recess including a plurality of stacked groups of layers, each group of layers of the superlattice channel comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions; and forming a replacement gate over the superlattice channel and removing the dielectric layer. |
地址 |
Wellesley Hills MA US |