Method for Forming Interconnect Structure that Avoids via Recess

摘要

A method for forming an interconnect structure includes forming a dielectric material layer on a semiconductor substrate. The dielectric material layer is patterned to form a plurality of vias therein. A first metal layer is formed on the dielectric material layer, wherein the first metal layer fills the plurality of vias. The first metal layer is planarized so that the top thereof is co-planar with the top of the dielectric material layer to form a plurality of first metal features. A stop layer is formed on top of each of the plurality of first metal features, wherein the stop layer stops a subsequent etch from etching into the plurality of the first metal features.

主权项

1. A semiconductor structure, comprising:
a dielectric material layer consisting of a dielectric material disposed over a semiconductor substrate; first metal features embedded in the dielectric material layer, wherein a surface of the first metal features facing away from the semiconductor substrate is substantially co-planar with a surface of the dielectric material layer facing away from the semiconductor substrate; a barrier layer interposed between the dielectric material layer and each of the first metal features on the bottom and sidewalls thereof; and a stop layer comprising an electrically conductive material formed on the top of each of the first metal features and on top of the barrier layer of each of the first metal features, the stop layer not extending substantially over the dielectric material layer.