INTERRUPTION FACILITY FOR ADJUNCT PROCESSOR QUEUES

摘要

Interruption facility for adjunct processor queues. In response to a queue transitioning from a no replies pending state to a reply pending state, an interruption is initiated. This interruption signals to a processor that a reply to a request is waiting on the queue. In order for the queue to take advantage of the interruption capability, it is enabled for interruptions.

主权项

1. A computer program product for executing a machine instruction, the computer program product comprising:
a computer readable storage medium readable by a processor and storing instructions for execution by the processor for performing a method comprising:
obtaining, by a central processing unit, a machine instruction for execution, the machine instruction comprising an opcode field specifying a process adjunct processor queue operation, the machine instruction to enable or disable interrupts for a queue; andexecuting the machine instruction, the executing comprising:
determining whether the queue is to be enabled for interrupts, the queue being associated with an adjunct processor coupled to the central processing unit; andbased on the determining indicating the queue is to be enabled for interrupts:
setting an enablement indicator of the queue; andsignaling to the adjunct processor that the queue is enabled for interrupts allowing the adjunct processor to generate an interrupt to the central processing unit for the queue.