COMPACT LOGIC EVALUATION GATES USING NULL CONVENTION

摘要

Compact logic evaluation gates are built using null convention logic (NCL) circuits. The inputs to a null convention circuit include a NCL true input and a NCL complement input. The NCL circuit includes a gate coupled to the pair of inputs, where the gate comprises a plurality of transistors. The transistors allow for logical signal capture, provide a pair of cross-coupled inverters for data storage, and include a first and second pull-down device. The first pull-down device causes a first side of the pair of cross-coupled inverters to go to a “0” state when a “1” is applied to the NCL true input, and the second pull-down device causes a second side of the pair of cross-coupled inverters to go to a “0” state when a “1” is applied to the NCL complement input.

主权项

1. A logic circuit comprising:
a pair of inputs where the pair of inputs comprise a null convention logic true input and a null convention logic complement input; a gate, coupled to the pair of inputs, comprised of a plurality of transistors where:
the plurality of transistors provide for logical signal capture;the plurality of transistors include a pair of cross-coupled inverters;the plurality of transistors include a first pull-down device with a transistor-gate node coupled to the null convention logic true input;the plurality of transistors include a second pull-down device with a transistor-gate node coupled to the null convention logic complement input;a “1” on the null convention logic true input causes a first side of the pair of cross-coupled inverters to go to a “0” state; anda “1” on the null convention logic complement input causes a second side of the pair of cross-coupled inverters to go to a “0” state.